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this document contains detailed information on power considerations, dc/ac electrical characteristics, and ac timing speci?ations for the mc92460 multichannel hdlc controller. the following topics are addressed: topic page section 1.1, ?eatures 2 section 1.2, ?lectrical and thermal characteristics 4 section 1.2.1, ?c electrical characteristics 4 section 1.2.2, ?hermal characteristics 6 section 1.2.3, ?ower considerations 6 section 1.2.4, ?ower dissipation 6 section 1.2.5, ac speci?ations 7 section 1.2.5.1, ?ysclk timing 7 section 1.2.5.2, ?xclk timing 7 section 1.2.5.3, ac timing 8 section 1.3, ?inout 11 a d v ance in f ormation MC92460EC/d r e v . 1.0, 7/2002 mc92460 hdlc controller hard w are speci f cations ncsd applications
2 mc92460 hdlc controller hardware speci cations motorola features figure 1 shows a block diagram of the mc92460. figure 1. mc92460 block diagram 1.1 features the following is an overview of the mc92460 feature set: channels 40 full-duplex hdlc channels programmable channel assignment (any logical channel to any signal) each channel has a default of 64 buffer descriptors (rx and tx) but the number of buffer descriptors per channel is con?urable controllers maximum throughput of 1919 mbps; individual controllers operate up to 66.7 mbps all communication controllers operate asynchronously programmable frame size (maximum 65,535 bytes) transparent memory access with internal memory controller 60x bus mc92460 directly connects with a 64-bit data and 32-bit address 60x bus supports 66.7 mhz 60x bus speed, with aggregate bandwidth of up to 1919 mbps depending register interrupt bus interface mpc8260 dual-port ram 32 kbyte scu 32-byte x 80 fifo communication buffer (64-bit x 4kw) bist sram dma arbiter 60x bus master interface unit 64-bit 66.7 mhz 3.3v rx fifo tx fifo flag/abort/idle 0-insert/delete 16 / 32 crc plls hdlc rxsd rxck txck txsd jtag 40 channels x 2 64-bit mc92460 two or more mc92460s
motorola mc92460 hdlc controller hardware speci cations 3 features on the type of main memory used up to four mc92460s may be connected in parallel on the 60x bus bus supports multiple master design communication buffers data buffer 256 kbits on-chip memory for data buffers 256 kbit communication buffer can store up to 819 bytes per frame. 80 channel virtual dma functionality executes between off-chip memory and the communication buffer bd buffer 32 kbyte on-chip dual-port ram for buffer descriptors a total of 4096 buffer descriptors (2048 txbd and 2048 rxbd) jtag support supports the ieee1149.1 jtag controller standard power and clocks supports single-beat and burst accesses on-chip pll for baud rate generator (maximum of 66.7 mhz) separate power supplies for core internal logic (1.8v) and for i/o (3.3v) package 480 pin tpga, 1.27 mm pitch
4 mc92460 hdlc controller hardware speci cations motorola electrical and thermal characteristics 1.2 electrical and thermal characteristics this section provides ac and dc electical speci?ations and thermal characteristics for the mc92460. 1.2.1 dc electrical characteristics this section describes the dc electrical characteristics for the mc92460. table 1 shows the maximum electrical ratings. table 2 lists recommended operational voltage conditions. this device contains circuitry protecting against damage due to high static voltage or electrical ?lds; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (either gnd or v cc ). table 3 shows dc electrical characteristics. table 1. maximum temperatures and voltages rating symbol value name unit core supply voltage vdd -0.3 ? 2.5 v i/o supply voltage vddh -0.3 ? 3.6 v input voltage vin gnd-0.3 ? 3.6 v junction temperature tj 120 o c storage temperature range t stg -55 ? 150 o c ambient temperature t a -40 ? 85 o c table 2. recommended operating conditions rating symbol value unit core supply voltage vdd 1.65 ? 1.95 v i/o supply voltage vddh 3.15 ? 3.465 v input voltage vin gnd -0.3 ? 3.6 v junction temperature tj 105 o c table 3. dc electrical characteristics ta=0 to 85c; vdd=2.05% vdc; vddh=3.35% vdc; gnd=0vdc; load capacitance < 10pf characteristics conditions symbol min max unit input high voltage v ih 2.0 3.465 v input low voltage v il gnd 0.8 v input leakage current v in =vddh i in ?10ua hi-z leakage current v in =vddh, gnd i oz ?10 + 10 ua signal low input current v il =0.8v i il ?60ua signal high input current v ih =2.0v i ih ?60ua output high voltage i oh =-7.0ma v oh 2.4 - v
motorola mc92460 hdlc controller hardware speci cations 5 electrical and thermal characteristics output low voltage br bg abb ts a[0-31] ap[0-3] ape tt[0-4] tbst tsiz[0-2] gbl ci wt lbclaim bto int tc[0-1] aack artry dbg dbwo dbb dh[0-31],dl[0-31] dp[0-7] dpe dbdis ta drtry tea i ol =7.0ma v ol 0.4 v output low voltage rx clk[0-39] tx clk[0-39] tx sd[0-39] tdo sbg sdbg sbr sirq cs0 cs1 cs2 i ol =5.0ma v ol 0.4 v table 3. dc electrical characteristics (continued) ta=0 to 85c; vdd=2.05% vdc; vddh=3.35% vdc; gnd=0vdc; load capacitance < 10pf
6 mc92460 hdlc controller hardware speci cations motorola electrical and thermal characteristics 1.2.2 thermal characteristics table 4 describes thermal characteristics. lfm = linear feet per minute 1.2.3 power considerations the average chip-junction temperature, tj, can be obtained from the following: where = package thermal resistance, junction to ambient, o c/w = ambient temperature, o c power equations are the following: = chip total power dissipation, w = chip core power, w = user-determined power dissipation on input/output pins, w 1.2.4 power dissipation table 5 describes maximum chip core power dissipation. table 4. maximum temperatures and voltages characteristics symbol thermal resistance value unit air flow thermal resistance for 480 tbga 10.48 o c/w 0 lfm 8.61 o c/w 100 lfm 7.78 o c/w 200 lfm 6.89 o c/w 400 lfm 5.52 o c/w 800 lfm table 5. maximum core power dissipation (p vdd ) vdd(v) sysclk frequency (mhz) i vdd (ma) p vdd (mw) p vddh (mw) 1.95 66.7 650 980 920 ja t j t a p d ja ? () + = ja t a p d p vdd p vddh + = p vdd i vdd vdd = p vddh i vddh vdd h =
motorola mc92460 hdlc controller hardware speci cations 7 electrical and thermal characteristics 1.2.5 ac speci cations these ac speci?ations are target speci?ations. 1.2.5.1 sysclk timing table 6 shows the system clock timing. figure 2 shows the sysclk. figure 2. sysclk 1.2.5.2 exclk timing table 7 shows the external clock timing. table 6. clock timing characteristics symbol min max unit operation frequency f 60.0 66.7 mhz clock period 15.0 16.7 ns clock pulse width t cl ,t ch 78ns sysclk input high voltage v ihc 2.4 3.465 v sysclk input low voltage v ilc gnd 0.4 v sysclk jitter 200 ps table 7. clock timing characteristics symbol min max unit operation frequency f 14.0 16.0 mhz clock duty 40 60 % clock pulse width t cl ,t ch 25 42.8 ns exclk input high voltage v ihc 2.4 3.465 v exclk input low voltage v ilc gnd 0.4 v exclk jitter + 200 ps sysclk t ch t cl t cyc
8 mc92460 hdlc controller hardware speci cations motorola electrical and thermal characteristics figure 3 shows the exclk. figure 3. exclk 1.2.5.3 ac timing figure 4 shows the hdlc external clock with polarity not inverted. all time speci?ations were measured at expected load capacitance c l =8pf. figure 4. hdlc external clock figure 5 shows an hdlc internal clock (txck/rxck output mode) whose polarity is not inverted. figure 5. hdlc internal clock table 8 shows the ac electrical characteristics. the frequency is 20 mhz. table 8. ac electrical characteristics spec num characteristic min max unit s1 hdlc input- external clock setup time 2 ns exsclk t ch t cl t cyc serial ck in input signal output signal s1 h1 s2 rxck0-39 txck0-39 and rxsd0-39 txsd0-39 serial ck out input signal output signal s3 h3 s4 txsd0-39 rxck0-39 txck0-39 and rxsd0-39
motorola mc92460 hdlc controller hardware speci cations 9 electrical and thermal characteristics figure 6 shows the interaction of several bus signals. figure 6. bus signals h1 hdlc input -external clock hold time 1 ns s2 hdlc output- external clock setup time 14 ns s3 hdlc input- internal clock setup time 12 ns h3 hdlc input- internal clock hold time 0 ns s4 hdlc output- internal clock setup time 4 ns table 8. ac electrical characteristics sysclk in ta input signal data bus input s10 h10 s11 h11 all_other_ input s12 h12 aack/ta/tea_output s13, s13? br/bg/dbg/sbg/sdbg_output s14 data bus output s15 all_other_output s16
10 mc92460 hdlc controller hardware speci cations motorola electrical and thermal characteristics table 9 shows the bus signal i/o characteristics. the frequency is 20 mhz. table 9. bus input/output characteristics spec num characteristic min max unit s10 ta/tea input 6 ns h10 ta/tea input 1 ns s11 data bus input signals 7 ns h11 data bus input signals 1 ns s12 all other input signals 7 ns h12 all other input signals 1 ns s13 aack/tea output 1 7 ns s13? ta output 1 8.5 ns s14 br/bg/dbg/sbg/sdbg output 1 7 ns s15 data bus output signals 1 8.5 ns s16 all other output signals 1 7 ns
motorola mc92460 hdlc controller hardware speci cations 11 pinout 1.3 pinout table 10. pin assignments ball a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ball 1 powvdd5 powvdd6 powvdd30 dp3 coregnd0 corevdd0 ar tr y tt2 powgnd2 sbg powgnd3 a8 sbr a15 corevdd2 a18 a22 a25 a29 int bto ap1 csa4 csa7 corevdd4 txsd0 powvdd31 powvdd13 powvdd12 1 2 powvdd7 powvdd4 dp1 dp2 powgnd0 ts aa ck dpe sdbg a1 a4 a7 a11 a12 coregnd2 a21 corevdd20 a26 a30 corevdd3 csa6 ap2 powgnd10 tc1 sysclk acoregnd1 txsd1 powvdd11 powvdd14 2 3 powvdd29 dp5 powvdd3 dp0 tsiz0 dbg abb tt0 tt4 coregnd1 corevdd1 br a10 powgnd5 a17 a19 a23 a27 powgnd8 sirq ap0 ape mode coregnd4 acorevdd1 rxck0 powvdd10 txck1 powvdd32 3 4 dp4 d55 d8 powvdd2 t a tsiz1 g_dbg powgnd1 tt3 a0 a3 a6 powgnd4 a14 a16 powgnd6 a24 a28 a31 lbclaim powgnd9 wt gbl txck0 rxsd0 powvdd9 rxsd1 txck2 txsd2 4 5 d31 d39 d47 d0 powvdd1 tbst tsiz2 bg tt1 dbb a2 a5 a9 a13 coregnd20 a20 powgnd7 tea coregnd3 dr tr y ap3 ci tc0 pll1o powvdd8 rxck1 csa8 rxck2 txsd3 5 6 coregnd19 d23 corevdd25 powgnd35 d63 powgnd11 rxsd2 corevdd5 txck3 rxck3 6 7 d54 d62 powgnd34 d15 corevdd19 coregnd5 rxsd3 txck4 rxsd4 rxck4 7 8 powgnd33 d30 coregnd25 d46 d7 txsd4 txsd5 txck5 rxck5 powgnd12 8 9 d61 d6 d14 d22 d38 rxsd5 txsd6 txck6 coregnd21 rxck6 9 10 d45 powgnd32 d53 corevdd18 dp6 rxsd6 txsd7 txck7 coregnd6 rxsd7 10 11 d21 dp7 d29 coregnd18 d37 rxck7 corevdd6 txsd8 txck8 rxsd8 11 12 d52 d60 d5 powgnd31 d13 rxck8 txsd9 txck9 rxsd9 rxck9 12 13 d28 powgnd30 d36 d44 scan_out_i powgnd13 txsd10 txck10 corevdd21 rxsd10 13 14 corevdd17 d20 d4 d40 d12 txsd11 txck11 rxsd11 rxck10 rxck11 14 15 d59 coregnd17 powgnd29 d43 d51 txck12 coregnd7 rxsd12 txsd12 corevdd7 15 16 d35 powgnd28 corevdd24 d27 d19 rxsd13 txck13 txsd13 rxck13 rxck12 16 17 d11 d3 d58 coregnd24 d50 rxsd14 coregnd22 txck14 txsd14 powgnd14 17 18 d42 powgnd27 d34 d26 d18 rxck15 rxsd15 txck15 txsd15 rxck14 18 19 d32 d10 corevdd16 d2 powgnd26 rxck16 coregnd8 rxsd16 txck16 txsd16 19 20 d57 coregnd16 d49 d41 d33 powgnd15 rxsd17 txck17 corevdd8 txsd17 20 21 corevdd23 d25 powgnd25 d17 d16 txsd19 corevdd22 txck18 txsd18 rxck17 21 22 d9 d1 d56 d48 d24 rxsd20 rxsd19 txck19 rxck18 rxsd18 22 23 powgnd24 scan_out_h scan_out_g scan_out_f cs0 corevdd9 txsd21 txck20 txsd20 rxck19 23 24 coregnd23 cs1 corevdd15 csa2 cs2 rxsd22 powgnd16 coregnd9 txck21 rxck20 24 25 powgnd23 coregnd15 scan_out_j scan_out_l powvdd22 amode corevdd14 csa0 tms acoregnd2 txck39 txck38 txck37 rxck35 rxck34 rxck33 txck32 txsd31 txck30 txck29 rxck27 scan_in_k coregnd10 txck24 powvdd15 rxck22 txsd22 rxck21 rxsd21 25 26 scan_out_e scan_out_k powgnd22 powvdd23 smode1 scan_out_d coregnd14 hreset tdo rxck39 coregnd13 powgnd20 txsd37 rxsd35 rxsd34 powgnd19 rxsd32 txck31 corevdd11 rxck29 rxsd28 txck27 corevdd10 txck25 txsd24 powvdd16 txsd23 txck22 scan_in_j 26 27 powvdd36 test0 powvdd24 smode0 test3 dbw o dbdis tdi exclk corevdd13 txsd39 txsd38 rxck36 txck35 scan_out_b txsd34 rxck32 rxsd31 rxsd30 powgnd18 rxck28 rxsd27 rxsd26 txsd26 txsd25 rxck23 powvdd17 txck23 powvdd33 27 28 powvdd28 powvdd25 test2 por csa3 powgnd21 test1 trst acorevdd2 rxsd39 rxck38 rxck37 rxsd36 txsd36 coregnd12 rxsd33 txsd33 rxck31 scan_out_a txsd30 txsd29 txsd28 rxck26 powgnd17 rxsd25 rxck24 rxsd23 powvdd18 powvdd20 28 29 powvdd26 powvdd27 powvdd35 sen csa5 csa1 pcmd tck pll2o scan_out_c rxsd38 rxsd37 txck36 corevdd12 txsd35 txck34 txck33 txsd32 rxck30 coregnd11 rxsd29 txck28 txsd27 txck26 rxck25 rxsd24 powvdd34 powvdd21 powvdd19 29 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj
MC92460EC/dec/d how to reach us: usa/europe/locations not listed: motorola literature distribution p.o. box 5405, denver, colorado 80217 1-303-675-2140 or 1-800-441-2447 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu minato-ku tokyo 106-8573 japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre, 2 dai king street tai po industrial estate, tai po, n.t., hong kong 852-26668334 technical information center: 1-800-521-6274 home page: http://www.motorola.com/semiconductors document comments: fax (512) 933-2625 attn: ncsd applications engineering information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and speci cally disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or speci cations can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of cers, employees, subsidiaries, af liates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the u.s. patent and trademark of ce. digital dna is a trademark of motorola, inc. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/af rmative action employer. ? motorola, inc. 2002

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